Application Domain
Functionality required to execute high performance SIP
Starting point: VSIPL forum's "Core Plus"
Hardware Domain
Programmable processors
VSIPL hardware as currently scoped
Plus parallel processors:
Distributed memory
Shared memory
Hybrid distributed/shared memory
Mapping
In library vs. in application
Library overhead
How to interface with user
Scope (SPMD/MIMD)
Support of flow graph
Different approaches
Separate maps (PVL/POOMA)
Compiler pragmas (OpenMP)
External tool (SAGE, RTExpress, Virtuoso, É)
Reference Implementation
Yes! Open Source.
Reconfiguration
Allocation to different modes
Static (i.e. pre-tested)
Dynamic (i.e. discovered)
Reactive response to hardware
Proactive response for performance
Threads
Yes
Memory Abstraction
Contiguous block
Grid
Hybrid grid/block
Global vs. local
Stride
Offset
Replicated objects
Overlapping data
Components
Interface to CORBA, COM
Reliability/Availability
Self-test
Exception management
Fault Tolerance
Data Permutation
DRI functionality
What role for DRI?
Compatible / incompatible with Parallel VSIPL?
Compatibility
Upward (old -> new)
Downward (new -> old)
Sideways (library -> library)
C binding
Data layout
Single processor -> multi processor
Compiler support
What capabilities are available
Allow for 18 month lead time
Level of Abstraction
For example A = B + C*D
where A, B, C and D are vectors/matrices.h
Adoption Incentives
Vendor (new markets)
Integrator (demonstrations)
Test suite
Compliance (to what level?)
Performance?
Local knowledge
Path to opt out of library space
Ability to use other components where needed
(e.g. which node am I?)
Tools
Profilers
Timers
Add flow graph features to UML
Interface with toolmakers
Early binding
Computation
Communication
Self-optimization
Degrees of ...
Extensibility
Abstract class library
Compile time and run time polymorphism
QoS
Predictability / bounded performance
Dialogue with vendors
