The primary findings of the workshop was the identification of the key technical issues involved in developing VSIPL++ and Parallel VSIPL. These issues are highly interconnected and be categorized in numerous ways.  In terms of their impact on the core HPEC-SI goals the issues are:

Portability:
  Memory, Mapping, Compatibility, Test suite, Components

Productivity:
  Adoption, Data Permutation, Compilers, Tools, Extensibility

Performance:
  Early Binding, Local Knowledge, Reconfiguration, Threads,
  Reliability / Availability, QoS

In terms of their functionality these issues are:

Ways of distributing work out amongst processors:
  Mapping, Threads, Memory abstraction, Components, Data permutation

When/how/how flexibly do we associate processes to processors:
  Reconfigurability, Reliability/FT, Early binding

Flexibility and extensibility of the middleware infrastructure:
  Compatibility, Test suite, Extensibility, Local knowledge

Tools and environments supporting rapid development of RT applications:
  Compiler support, Tools, Quality of service

Marketing and tech transition/transfer:
  Adoption, Reference implementation