High Performance Embedded Computing
Software Initiative (HPEC-SI)

        OUT POSITIONS:
To further focus these Technical Issues the Workshop tried to develop "out positions" regarding each of these issues.  These statements are positions that need to be explicitly addressed either positively or negatively.
    Memory
      Modify underlying definitions of VSIPL blocks and views
      to preserve abstract qualities and support parallel data.

    Mapping
      At the application level mapping information should appear
      to be orthogonal/independent of functionality,
      with the goal of supporting easy scaling and dynamic mapping, i.e.
      POOMA/PVL/SPE convention, in contrast to inside code
      (e.g OpenMP) or not at all (e.g. parallelism discovered automatically),

    Compatibility
      Provide a clear path upward.
      Provide easy "opt out" mechanism.

    Reshaping
      Transparent support for DRI-like functionality.

    Adoption
      Seek out demos and show real application performance.
      Seek out new markets (medical, software radio, telecom).

    ACTION ITEMS

    At first glance, the HPEC-SI Development and Prototype working groups are dealing with separable areas (VSIPL++ vs. Parallel VSIPL).  However, it became clear in the workshop that two fundamental issues intrinsically link these two areas: Memory Model and Parallel Mapping.  Initial positions on these two areas need to be developed in order for VSIPL++ to begin in a way that will be readily extensible and compatible with Parallel VSIPL.

    To address the issues of Memory Model and Parallel Mapping it is clear
    that collective education needs to be undertaken on the different
    approaches. To facilitate this we need to take the following action:

    • Open technical meeting in June focused on these two issues.
    • A prerequisite of this meeting is the delivery to the current workshop

    • attendees of the following information:
                C++ VSIPL bindings by MPI Soft Tech
                   -API documents
                   -Source code
                 Parallel Vector Library (PVL) by MIT/LL
                   -Design documents
                   -Reference manual
                   -Source code
                 Additional documents on relevant aspects of:
                   -LANL POOMA
                   -DRI
                   -SPE
                 Book References

    Where possible, this information will be made available on the web by GTRI.

    In addition to the next Development/Prototype Working Group meeting we will also have:
     

    • Technical Advisory Board meeting at the SIP Forum in Biloxi
    • Demonstration Working Group kickoff
    • Stakeholders and potential new sponsors meeting