HPEC-SI DEVELOPMENT WORKING GROUP (November 12, 2003 Wednesday)
APPLIED RESEARCH WORKING GROUP and VSIPL FORUM (November 13, 2003, Thursday)

MINUTES

LOCATION: MIT Lincoln Laboratory, Lexington, MA
Room S2-616
For directions see
http://www.ll.mit.edu/about/visitor.html

ORGANIZERS:

HPEC-SI Development Working Group Co-Chairs
Mark Richards (mark.richards@gtri.gatech.edu)
James Lebak (jlebak@ll.mit.edu)

HPEC-SI Prototypes Working Group Co-Chairs
Bob Bond (rbond@ll.mit.edu)
Ken Flowers (kflowers@mc.com)

HPEC-SI Advisory Board
Jeremy Kepner (kepner@ll.mit.edu)

ATTENDANCE:
Attendance is open to all U.S. Citizens.
If you plan on attending (in person or telecon) please send e-mail to:
kepner@ll.mit.edu

AGENDA:

Wednesday, Nov 12, 2003
(DEVELOPMENT WORKING GROUP)
09:00-09:30 BREAKFAST
09:30-10:00 HPEC-SI Overview (Kepner MIT-LL) PPT / PDF
10:00-12:00 VSIPL++ Specification Review
- Vote 2004 Status (Kepner Lincoln
- Status of VSIPL++ compilation on embedded platforms (Leimbach MSTI)PDF
- Advanced Block functionality (Campbell/GTRI) & workaround writeup PPT / PDF
- VSIPL++ Implementation Status (Oldham/CodeSourcery) PPT / PDF
12:00-01:00 LUNCH
01:00-02:00 Subviews & PETE Replacement (Rutledge/MIT-LL) PPT / PDF
02:00-03:00 ||VSIPL++ User API (Oldham/Codesourcery) PPT / PDF
03:00-03:30 BREAK
03:30-04:00 DRI Overlap Parallel Support Levels (Cain/Mercury) PDF
............DRI Blocks (Paavola/SKY Computers)PPT / PDF
04:00-04:30 Aegis Demo (Kent Doss Cook /Lockheed Martin)
04:30-05:00 Coordinated Volunteerism update

Thursday, Nov 13, 2003
(APPLIED RESEARCH WORKING GROUP and VSIPL FORUM)
09:00-09:30 BREAKFAST
09:30-10:00 Task/Pipeline Parallelism Requirements (Rutledge) PPT / PDF
10:00-10:30 Task/Pipeline Prototyping in MatLab (Travinin) PPT / PDF
10:30-11:00 Fault Tolerance
||VSIPL++ Fault Tolerance Requirements (Skjellum/MSTI) PPT / PDF
11:00-12:00 VSIPL++ and FPGAs
- Miriam Leeser/Northeastern PPT / PDF
- Micheal Vai/Lincoln PPT / PDF
12:00-01:00 LUNCH & VSIPL Forum business