TOPIC: VSIPL++ & Parallel VSIPL Technical Issues:

• Memory Abstraction: How do we generalize the VSIPL ideas of "blocks" and "views" into object oriented/parallel concepts?
• Parallel Mapping: How do we described where data live and where operations take place in a parallel system?

LOCATION: MIT Lincoln Laboratory, Lexington, MA
                    Rooms S2-336 and S2-600B
                    For directions see
                  http://www.ll.mit.edu/about/visitor.html

ORGANIZERS:

HPEC-SI Development Working Group Co-Chairs
   Mark Richards (mark.richards@gtri.gatech.edu)
   James Lebak (jlebak@ll.mit.edu)

HPEC-SI Prototypes Working Group Co-Chairs
   Bob Bond (rbond@ll.mit.edu)
   John Reynders (john.reynders@celera.com)

HPEC-SI Advisory Board
   Jeremy Kepner (kepner@ll.mit.edu)