All,

The next HPEC-SI meeting will be on Wednesday and Thursday, June 13 - 14, 2007 at Lincoln Laboratory.  Below you will find a draft of the agenda.  Please let me know if there should be any changes.  If you are planning on attending, please RSVP to ssacco@ll.mit.edu.

Thanks,

Sharon

Minutes

-------------------------------------------------------

MEETING GOALS

(1) VSIPL++ status
(2) Review Parallel VSIPL++  Examples
(3) Conduit and Tasks
(4) FPGA API update
(5) Fixed Point proposal
(6) Image Processing update
(7) VSIPL meeting

-------------------------------------------------------

Wednesday, 13 June:

(DEMONSTRATION & DEVELOPMENT WORKING GROUPS)

09:00-09:30 BREAKFAST

09:30-10:00 HPEC-SI review & HPEC preview (Kepner) PPT | PDF

10:00-11:00 Demo/eval status (Pancoast, Judd, Sroka)

11:00-12:00 VSIPL++ Implementation Status (Bergmann)PPT | PDF

12:00-01:00 LUNCH

01:00-02:00 Conduits, Tasks, Quality of Service, Fault Tolerance Discussion (Schrader)

02:00-02:30 User’s Guide Update (Campbell)

02:30-03:00 BREAK

03:00-03:45 Simulink SAR example (Lebak)

03:45-04:30 Cell Programming Experiences (Marzilli, Geraci)

04:30-05:00 A High-Level Signal Processing Library for Multicore Processors (Sacco)PPT | PDF

Thursday, 14 June:

(APPLIED RESEARCH WORKING GROUP & VSIPL FORUM)

09:00-09:30 BREAKFAST

09:30-10:30 FPGA API update (Leeser)PPT | PDF
VForce (Lesser) PPT | PDF

10:30-10:45 Break

10:45-11:30 Fixed Point Spec (Moore)PPT | PDF

11:15-11:45 VSIPL image processing (Seetharaman AFIT, Palaniappan U. Missouri, Columbia)

11:45-12:00 Discussion

12:00-12:30 LUNCH

(VSIPL Forum)

12:30-02:00 VSIPL

- Variable length FFT spec (Sroka)

- Sort function (Judd)

- Early Binding for Interpolation (Judd)

ATTENDANCE:
Attendance is open to all U.S. Citizens. If you plan on attending (in person or telecon) please send e-mail to: ssacco@ll.mit.edu.